Network processors are often located on an I/O card which is distinct from a control complex card containing a control complex for controlling the network processor. When the network processor is started up, memory attached to the network processor is typically diagnosed and then a boot loader is loaded into the memory. In some systems, particularly legacy systems, the diagnosis and the loading of the boot loader is performed from the control complex.
A high speed bus, such as a PCI bus, provides fast access to the network processor. However the bus communicating between the cards, that is the control complex bus from the control complex card to the I/O card, is often much slower than the PCI bus. The control complex bus is usually a 16-bit asynchronous bus. The PCI bus is typically about 400 times the speed of the control complex bus. A bridge is provided on the I/O card for enabling communication between the control complex using the control complex bus and the network processor using the PCI bus.
In such systems diagnosis of the network processor memory is performed by writing known data to some or all of the memory locations, and then reading back the data from the memory locations and comparing the read values with those that were written. The slow speed of the control complex bus limits how such diagnosis can be carried out at any efficient speed. One solution is to have the control complex issue the write and read commands, but to only write data to a portion of the memory. Another solution is for the control complex to load a boot loader into the network processor, and then have the boot loader perform diagnosis on the memory. However this is complicated, and furthermore is slow due to the large size of the boot loader and the slow speed of the control complex bus. Another solution is build a boot loader ROM into the network processor. However this is expensive since a boot ROM part must be added to the I/O card. Furthermore, the boot loader ROM is typically located on the control complex card anyway, and so a second boot loader ROM may be unnecessary duplication.
Another problem arising from the slow control complex bus speed is the loading of software into the memory of the network processor. Writing of data into the memory requires that the writing of data be verified, in order to spot corruption that may have been missed during the diagnosis process. However verifying of written data requires two passes of data across the control complex bus, once when the data is being written to memory and once when the data is being read from memory. This is particularly a problem for a control complex which loads a boot loader into network processor memory, as the boot loader is typically large.
A solution which allowed diagnosis and verification of data writing to avoid the bottleneck of the control complex bus would increase the speed at which network processors could be started up, especially in legacy systems in which the control complex bus is much slower than the PCI bus which provides access to the network processor.